In complementary metal oxide semiconductor (CMOS) processing, sub-0.05 .mu.m field effect transistor (FET) devices must be fabricated using techniques in which the gate region is formed from an etch process that exhibits a high selectivity rate (&gt;30:1) while maintaining vertical sidewalls. One problem with using conventional processing is that n.sup.+ - and p.sup.+ -polysilicon have different etch rates; this results in the requirement of pre-doped polysilicon gate etch with even higher selectivity to oxide.
To avoid the above problem with prior art fabrication processes, a damascene technique is employed in fabricating the gate region of the CMOS structure. In the formation of a gate region utilizing a prior art damascene technique, a trough (or gate hole) is defined in a stack which consists of various material layers, e.g., A, B, C, etc. The material layers of the stack used for defining the trough, for example, layer A, is removed by employing a damage free process to maintain substrate integrity. Following subsequent processing steps that result in the trough being filled with a gate conductor, e.g., polysilicon, the gate conductor is polished back so that the gate conductor is planar with the top of material layer A. As indicated above, material layer A must be removed from the structure. Typically, the removal of this material layer is carried out utilizing a chemical etchant which is highly selective in removing the material layer as compared to the surrounding and/or underlying layers of the structure.
During the process of this removal, some of the gate conductor may be consumed. The consumption of some of the gate conductor during damascene etch back may effect the performance of the final device. An example of this is when material layer A of the stack is Si.sub.3 N.sub.4 and the removal process is carried out with a hot phosphoric acid wet etch. If the gate conductor is polysilicon that has various dopants embedded therein, the isotropic etch of the polysilicon could proceed at between 1/30 to 1/60 the rate of the nitride removal. The isotropic nature of such an etch would result in thickness and line width variances of the resulting conductive lines.
In view of the above-mentioned drawback with prior art damascene gate formation processes, there is a continued need for developing a new and improved damascene gate formation process wherein the material layers used in defining the gate region can be removed without adversely the gate conductor and/or the device performance properties of the resulting structure.